EDN

How To Interface DDR-II SRAMs with Stratix II Devices

Synchronous static RAM (SRAM) architectures are evolving to support the high-throughput requirements of communications, networking, and digital signal processing (DSP) systems. Previous Sync SRAM ...
eTeknix

ADATA Unveils its New ACE Series of DDR4/DDR5 Memory

As a creator, it is often necessary to switch between different applications to perform multiple tasks such as loading files, editing, rendering, or transferring files. What’s more, frequent software ...
EDN

Design tool yields DDR memory interface IP

The DDR PHY compiler is said to be the industry’s first DDR SDRAM design tool. It enables assembly of a complete, customized high-performance DDR PHY for ASICs, ASSPs, or SoC applications while ...
Electronic Design

DDR5 DRAM: How a New Interface Improves Performance with Less Power

Why a new memory interface is needed. Features and benefits of DDR5. How DDR5 will usher in a new era of composable, scalable data centers. The move to DDR5 will probably be more important than most ...
Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...