Open source software is popular – for operating systems as well as for office programs. But can this idea also work with hardware? We interviewed Rick O'Connor, Executive Director of the RISC-V ...

A job listing posted to Apple's website this week reveals the company is researching RISC-V instruction set architecture solutions, suggesting future in-house chip designs might implement the ...

A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. “Transport triggered architectures ...

RISC-V ISA (Instruction Set Architecture) is designed in a modular way. It means that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows ...

At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux ...

Microchip’s PolarFire® SoC FPGA Icicle Kit enables the broad RISC-V-based Mi-V ecosystem for the industry’s lowest-power FPGA CHANDLER, Ariz., Sept. 16, 2020 (GLOBE NEWSWIRE) -- The rising adoption of ...

Hsinchu, Taiwan, Mar. 12, 2019 – At the RISC-V Workshop Taiwan cohosted by Andes Technology today, Andes proudly announces the debut of its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors.

A computer processor uses a so-called Instruction Set Architecture to talk with the world outside of its own circuitry. This ISA consists of a number of instructions, which essentially define the ...

First and foremost, RISC-V is a modular, open-source, instruction set definition and nothing more. RISC-V as an ecosystem is much more. The instruction set provides the encoding and semantics, but it ...