Business Wire

Daniel Lustig, Chairman of the RISC-V Memory Model Task Group, Receives Inaugural 2018 RISC-V Foundation Board of Directors’ Award at the RISC-V Summit

BERKELEY, Calif. & SANTA CLARA, Calif.--(BUSINESS WIRE)--The RISC-V Foundation, the non-profit corporation controlled by its members to drive the adoption and implementation of the free and open ...
TweakTown

RISC-V systems support replacing RAM sticks WITHOUT powering off the system

The upcoming version 6.11 of the mainline Linux kernel has support for RISC-V memory hot plugging, meaning you can pull RAM sticks out of your PC without turning it off... very nice. The Linux kernel ...
Semiconductor Engineering

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)

A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. “Despite decades of ...
Semiconductor Engineering

Implementing Fast Barriers For A Shared-Memory Cluster Of 1024 RISC-V Cores

A technical paper titled “Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster” was published by researchers at ETH Zürich and Università di Bologna. “Synchronization ...
Design-Reuse

Slide Shows Samsung May be Developing a RISC-V CPU for In-memory AI Chip

Samsung may have unintentionally revealed its intent to develop a RISC-V CPU, which a presentation slide showed may be used in an AI chip. The company plans to release an AI accelerator with heavy ...
insideHPC

March 30: CHIPS Alliance and RISC-V International Invite the RISC-V Community to Update Unified Memory Architecture Standard

SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set ...
Design And Reuse

RISC-V and AI/ML redefining the future of Edge Computing

Easier multi-device coordination: RISC-V facilitates better coordination among multiple edge devices through its open ...
Liliputing

Bit-Brick Cluster K1 lets you build a 32-core RISC-V computer (by clustering 4 SpacemiT K1 boards)

At least that’s the idea behind the Bit-Brick Cluster K1. Real-world performance will obviously vary depending on the task. But for applications that support parallel processing, this cluster board ...
Forbes

Storage And Memory At The 2020 CES, Part 2

This piece talks about more of the storage and memory products and applications on display in exhibits and suites at the 2020 CES. In particular we will discuss SK hynix, Kingston, Gigabyte, OWC, ...
Hackaday

RISC-V: Why The ISA Battles Aren’t Over Yet

A computer processor uses a so-called Instruction Set Architecture to talk with the world outside of its own circuitry. This ISA consists of a number of instructions, which essentially define the ...
CNET

AMD's SSE5 ends the old RISC vs. CISC debate

Prompted by the chipmaker's announcement of the SSE5 instruction-set extensions, Glaskowsky analyzes the ultimate outcome to this old controversy. Peter N. Glaskowsky is a computer architect in ...
Electronic Design

NPU is Built Around RISC-V Core

IP that’s built on a RISC-V vector processing CPU. The platform has been augmented to support artificial-intelligence/machine ...